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7 startups approved for chip designing: Rajeev Chandrasekhar

7 startups approved for chip designing Rajeev Chandrasekhar
Photo Credit : IANS

Bengaluru: The government aims to build a robust, globally competitive presence in the global semiconductor ecosystem in the next 10 years and so far, seven chip design startups have been approved for funding and assistance in developing their products, Minister of State for Electronics and IT, Rajeev Chandrasekhar, said on Saturday.

In his address on the second day of ‘Semicon India 2023’, the minister said the future is bright for India in the global semiconductor ecosystem.

“So far, seven chip design startups have been approved for funding and assistance in developing their products. This initiative is steadily gaining confidence and support. It’s a relatively new opportunity for startups to delve into deep tech and semiconductor design,” he said.

The government has launched a Digital India RISC-V programme (DIR-V) and a large number of startups and incubation centres built around academic institutions are focusing on the future of RISC-V and on the devices it operates on, Chandrasekhar said.

On the second day of the conference, the CDAC announced a partnership with Arm, the world’s leading semiconductor IP company, to empower semiconductor startups in the country through the “Arm Flexible Access for Startups” programme.

“Innovative silicon startups will drive the future of the semiconductor industry as they develop life-changing new technologies in areas from AI to autonomous vehicles and IoT,” said Guru Ganesan, President, Arm India.

Two more startups/MSMEs involved in semiconductor design were announced as participants in the ‘SemiconIndia futureDESIGN DLI’ scheme.

One of them is Aheesa Digital Innovations Pvt Ltd (Aheesa) located in Chennai, which focuses on telecom, networking and cyber security domains. The other startup is Bengaluru-based Calligo Technologies which serves global companies in HPC, Big Data and AI/ML segments.

The DLI scheme aims to offer financial incentives as well as design infrastructure support across various stages of development and deployment of semiconductor designs for Integrated Circuits (ICs), Chipsets, System on Chips (SoCs), Systems & IP Cores and semiconductor linked design(s) over a period of five years.

A key collaboration was also initiated through a MoU between the Centre for Nano Science and Engineering (CeNSE) at the Indian Institute of Science (IISc), Bengaluru, and Lam Research India.

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